1. Field of the Invention
The present invention pertains to a method for adjusting a semiconductor device threshold voltage during device fabrication, and more particularly to adjusting the threshold voltage of an insulated gate field effect device by high energy ion implantation through the gate thereof.
2. Description of Related Art
The threshold voltage V.sub.t for MOSFET transistors is defined as the voltage V.sub.gs applied between gate and source, below which the MOS transistor drain-to-source current I.sub.ds becomes zero. The threshold voltage for n-channel and p-channel devices are denoted V.sub.tn and V.sub.tp, respectively. The threshold voltage is a function of a number of parameters, including the gate material, the gate insulation material, the gate insulator thickness, the channel doping, the impurities at the silicon-insulator interface, and the voltage V.sub.sb between the source and substrate.
Many integrated circuit designs use MOSFET devices with other device types or both high and low power PMOS and NMOS devices. For example, smart power devices generally include a variety of small signal analog and digital CMOS devices combined with DMOS transistors on the same substrate. When, for example, PMOS devices are formed with NMOS and DMOS devices in a D/CMOS process or with NPN devices in a BiCMOS process, the V.sub.tp of the PMOS devices is not as low as might be desired, especially for use with low voltage power supplies. For example, in a D/CMOS process for fabricating 15 volt devices in which the gate oxide thickness specification is 1,000 Angstroms (".ANG."), a typical PMOS transistor of 5 .mu.m p+ poly gate length exhibits a 2.5 volt threshold, which is acceptable for a 15 volt integrated circuit. In scaling such a process for a 5 or 12 volt power supply, the gate oxide specification is scaled to 580 .ANG. thickness. The NMOS threshold nicely reduces from 1.8 volts to 1.1 volts. Unfortunately, the improvement in PMOS threshold is considerably less, dropping from 2.5 volts to only 2.1 volts. This PMOS threshold is generally unsatisfactory for a 5 or 12 volt integrated circuit. Further thinning of the gate insulator thickness is undesirable since it limits the maximum allowable gate voltage. For example, a 300 .ANG. gate oxide may be safely operated only up to a maximum gate drive of 12 volts, leaving no margin for supply variations in a 12 volt system. Even if a 5 volt system is used, the threshold voltage remains above 1.4 volts due to oxide independent terms in the V.sub.t equation.
Known techniques for threshold adjust are not entirely satisfactory for use in some mixed device-type processes. For example, while the PMOS threshold in a D/CMOS can be reduced by using a more lightly doped n-well, the more lightly doped n-well results in lower punchthrough breakdown and adversely affects other device types for which the process is intended.
Channel doping is a well known technique for threshold adjustment. Channel doping involves varying the doping concentration at the silicon-insulator interface. In CMOS processes, channel doping typically is done prior to deposition of the gate polysilicon. Generally, the technique is not applicable to processes in which two and possibly more successive diffusions are used, such as processes that include steps for fabricating NPN devices in which a base must be diffused deeper than the emitter, and processes that include steps for fabricating DMOS devices in which a body region must be diffused deeper than a source. Impurity distribution in diffusion processes is dependent on the product of the diffusion coefficient D(T) and the time, or .sqroot.Dt (hereinafter "root Dt). In double-diffused and triple-diffused bipolar devices and double diffused MOSFET devices, the root Dt is large, ranging from 0.3 or 0.4 microns all the way down to 1.0 or 1.5 microns. When exposed to such large root Dt values, the threshold dopant diffuses too deeply into the substrate, forming a leakage path between the source and the drain of the MOSFET which is not pinched off at V.sub.gs =0.
The necessity for using only low temperature processing following the channel doping step has been a significant motivating factor in classical VLSI and integrated circuit process design. Unfortunately, flexibility of device type remains limited, particularly in analog integrated circuits or in power integrated circuits.
Another conventional technique for reducing V.sub.tp of a PMOS device, one which is useful even in processes having long diffusion times after the polysilicon deposition step, is to use boron-doped p-type polysilicon gates in association with the PMOS devices, instead of phosphorus doped n-type polysilicon gates. The p-type polysilicon has a different work function, so that the threshold of the PMOS devices is shifted by about a volt. Unfortunately, this technique is not entirely satisfactory for use in processes specifying a thin gate oxide, as the boron from the p-type polysilicon penetrates easily through the thin gate oxide in any subsequent diffusion steps and can counterdope the channel. Leakage and other problems result. Moreover, this problem is exacerbated by the presence of hydrogen. While the risk is reduced by the use of a thicker gate oxide, say on the order of 1000 .ANG., the requirement for a thicker gate oxide compromises process flexibility. Moreover, whether a thin or thick gate oxide is used, the design of CMOS inverters is complicated. Typically in a CMOS inverter, the interconnect between the PMOS and NMOS devices is formed by the polysilicon gates themselves. If n-type poly is associated with the n-channel devices and p-type poly is associated with the p-channel devices, a diode rather than a closed circuit forms where the two differently doped polysilicon gates abut. While this problem can be solved by the use of strapping metal to short out the diode, the fabrication of the strapping metal adds complexity to the process.
A need, therefor, exists for a technique for adjusting the V.sub.t of MOSFET devices in processes that allow fabrication of mixed device types, while preserving the ability to use long diffusion and high temperature steps subsequent to polysilicon gate deposition.